-- Company: 
-- Engineer: Ethan Longley
-- 
-- Create Date:  
-- Design Name: 
-- Module Name: Wallace_Tree
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision: 
-- Revision 0.01 - File Created 
-- Additional Comments: 
-- 
---------------------------------------------------------------------------------- 
 
 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
 
-- Uncomment the following library declaration if using 
-- arithmetic functions with Signed or Unsigned values 
-- use IEEE.NUMERIC_STD.ALL; 
 
-- Uncomment the following library declaration if instantiating 
-- any Xilinx leaf cells in this code. 
-- library UNISIM; 
-- use UNISIM.VComponents.all; 
 
entity Wallace_Tree is 
 Port (	A 	: in STD_LOGIC_VECTOR (7 downto 0) ; 
 	B 	: in STD_LOGIC_VECTOR (7 downto 0) ; 
 	P 	: out STD_LOGIC_VECTOR (15 downto 0)) ; 
end Wallace_Tree; 
 
architecture Behavioral of Wallace_Tree is 
component full_adder is 
 Port (	A 	: in STD_LOGIC; 
 	B 	: in STD_LOGIC; 
 	Cin 	: in STD_LOGIC; 
 	S 	: out STD_LOGIC; 
 	Cout 	: out STD_LOGIC); 
end component; 
 
component half_adder is 
 Port ( A : in STD_LOGIC; 
 	B : in STD_LOGIC; 
 	S : out STD_LOGIC; 
 	Cout : out STD_LOGIC); 
 end component; 
 
 signal 
S2,S3,S4,S5,S6,S7,S8,S10,S11,S12,S13,S14,S15,S16,S18,S19,S20,S21,S22,S23,S24,S26,S27,S28,S29,S30,S31,S32,S34,S35,S36,S37,S38,S39,S40,S42,S43,S44,S45,S46,S47,S48 : STD_LOGIC; 
 signal 
C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,C31,C32,C33,C34,C35,C36,C37,C38,C39,C40,C41,C42,C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55 : STD_LOGIC; 
 
 signal A1B0 : STD_LOGIC; 
 signal A2B0 : STD_LOGIC; 
 signal A3B0 : STD_LOGIC; 
 signal A4B0 : STD_LOGIC; 
 signal A5B0 : STD_LOGIC; 
 signal A6B0 : STD_LOGIC; 
 signal A7B0 : STD_LOGIC; 
 
 
 signal A0B1 : STD_LOGIC; 
 signal A1B1 : STD_LOGIC; 
 signal A2B1 : STD_LOGIC; 
 signal A3B1 : STD_LOGIC; 
 signal A4B1 : STD_LOGIC; 
 signal A5B1 : STD_LOGIC; 
 signal A6B1 : STD_LOGIC; 
 signal A7B1 : STD_LOGIC; 
 
 signal A0B2 : STD_LOGIC; 
 signal A1B2 : STD_LOGIC; 
 signal A2B2 : STD_LOGIC; 
 signal A3B2 : STD_LOGIC; 
 signal A4B2 : STD_LOGIC; 
 signal A5B2 : STD_LOGIC; 
 signal A6B2 : STD_LOGIC; 
 signal A7B2 : STD_LOGIC; 
 
 signal A0B3 : STD_LOGIC; 
 signal A1B3 : STD_LOGIC; 
 signal A2B3 : STD_LOGIC; 
 signal A3B3 : STD_LOGIC; 
 signal A4B3 : STD_LOGIC; 
 signal A5B3 : STD_LOGIC; 
 signal A6B3 : STD_LOGIC; 
 signal A7B3 : STD_LOGIC; 
 
 signal A0B4 : STD_LOGIC; 
 signal A1B4 : STD_LOGIC; 
 signal A2B4 : STD_LOGIC; 
 signal A3B4 : STD_LOGIC; 
 signal A4B4 : STD_LOGIC; 
 signal A5B4 : STD_LOGIC; 
 signal A6B4 : STD_LOGIC; 
 signal A7B4 : STD_LOGIC; 
 
 signal A0B5 : STD_LOGIC; 
 signal A1B5 : STD_LOGIC; 
 signal A2B5 : STD_LOGIC; 
 signal A3B5 : STD_LOGIC; 
 signal A4B5 : STD_LOGIC; 
 signal A5B5 : STD_LOGIC; 
 signal A6B5 : STD_LOGIC; 
 signal A7B5 : STD_LOGIC; 
 
 signal A0B6 : STD_LOGIC; 
 signal A1B6 : STD_LOGIC; 
 signal A2B6 : STD_LOGIC; 
 signal A3B6 : STD_LOGIC; 
 signal A4B6 : STD_LOGIC; 
 signal A5B6 : STD_LOGIC; 
 signal A6B6 : STD_LOGIC; 
 signal A7B6 : STD_LOGIC; 
 
 signal A0B7 : STD_LOGIC; 
 signal A1B7 : STD_LOGIC; 
 signal A2B7 : STD_LOGIC; 
 signal A3B7 : STD_LOGIC; 
 signal A4B7 : STD_LOGIC; 
 signal A5B7 : STD_LOGIC; 
 signal A6B7 : STD_LOGIC; 
 signal A7B7 : STD_LOGIC; 
 
begin 
A1B0 <= A(1) and B(0); 
A2B0 <= A(2) and B(0); 
A3B0 <= A(3) and B(0); 
A4B0 <= A(4) and B(0); 
A5B0 <= A(5) and B(0); 
A6B0 <= A(6) and B(0); 
A7B0 <= A(7) and B(0); 
 
A0B1 <= A(0) and B(1); 
A1B1 <= A(1) and B(1); 
A2B1 <= A(2) and B(1); 
A3B1 <= A(3) and B(1); 
A4B1 <= A(4) and B(1); 
A5B1 <= A(5) and B(1); 
A6B1 <= A(6) and B(1); 
A7B1 <= A(7) and B(1); 
 
A0B2 <= A(0) and B(2); 
A1B2 <= A(1) and B(2); 
A2B2 <= A(2) and B(2); 
A3B2 <= A(3) and B(2); 
A4B2 <= A(4) and B(2); 
A5B2 <= A(5) and B(2); 
A6B2 <= A(6) and B(2); 
A7B2 <= A(7) and B(2); 
 
A0B3 <= A(0) and B(3); 
A1B3 <= A(1) and B(3); 
A2B3 <= A(2) and B(3); 
A3B3 <= A(3) and B(3); 
A4B3 <= A(4) and B(3); 
A5B3 <= A(5) and B(3); 
A6B3 <= A(6) and B(3); 
A7B3 <= A(7) and B(3); 
 
A0B4 <= A(0) and B(4); 
A1B4 <= A(1) and B(4); 
A2B4 <= A(2) and B(4); 
A3B4 <= A(3) and B(4); 
A4B4 <= A(4) and B(4); 
A5B4 <= A(5) and B(4); 
A6B4 <= A(6) and B(4); 
A7B4 <= A(7) and B(4); 
 
A0B5 <= A(0) and B(5); 
A1B5 <= A(1) and B(5); 
A2B5 <= A(2) and B(5); 
A3B5 <= A(3) and B(5); 
A4B5 <= A(4) and B(5); 
A5B5 <= A(5) and B(5); 
A6B5 <= A(6) and B(5); 
A7B5 <= A(7) and B(5); 
 
A0B6 <= A(0) and B(6); 
A1B6 <= A(1) and B(6); 
A2B6 <= A(2) and B(6); 
A3B6 <= A(3) and B(6); 
A4B6 <= A(4) and B(6); 
A5B6 <= A(5) and B(6); 
A6B6 <= A(6) and B(6); 
A7B6 <= A(7) and B(6); 
 
A0B7 <= A(0) and B(7); 
A1B7 <= A(1) and B(7); 
A2B7 <= A(2) and B(7); 
A3B7 <= A(3) and B(7); 
A4B7 <= A(4) and B(7); 
A5B7 <= A(5) and B(7); 
A6B7 <= A(6) and B(7); 
A7B7 <= A(7) and B(7); 
 
-- Stage 1 
 
P0 	: P(0) <= A(0) and B(0) ; 
 
ha11 	: half_adder port map(A1B0,A0B1,P(1),C1); 
fa12 	: full_adder port map(A2B0,A1B1,A0B2,S2,C2); 
fa13 	: full_adder port map(A3B0,A2B1,A1B2,S3,C3); 
fa14 	: full_adder port map(A4B0,A3B1,A2B2,S4,C4); 
fa15 	: full_adder port map(A5B0,A4B1,A3B2,S5,C5); 
fa16 	: full_adder port map(A6B0,A5B1,A4B2,S6,C6); 
fa17 	: full_adder port map(A7B0,A6B1,A5B2,S7,C7); 
ha18 	: half_adder port map(A7B1,A6B2,S8,C8); 
 
-- Stage 2
ha21 	: half_adder port map(S2,C1,P(2),C9); 
fa22 	: full_adder port map(S3,C2,A0B3,S10,C10); 
fa23 	: full_adder port map(S4,C3,A1B3,S11,C11); 
fa24 	: full_adder port map(S5,C4,A2B3,S12,C12); 
fa25 	: full_adder port map(S6,C5,A3B3,S13,C13); 
fa26 	: full_adder port map(S7,C6,A4B3,S14,C14); 
fa27 	: full_adder port map(S8,C7,A5B3,S15,C15); 
fa28 	: full_adder port map(A7B2,C8,A6B3,S16,C16); 
 
-- Stage 3
ha31 	: half_adder port map(S10,C9,P(3),C17); 
fa32 	: full_adder port map(S11,C10,A0B4,S18,C18); 
fa33 	: full_adder port map(S12,C11,A1B4,S19,C19); 
fa34 	: full_adder port map(S13,C12,A2B4,S20,C20); 
fa35 	: full_adder port map(S14,C13,A3B4,S21,C21); 
fa36 	: full_adder port map(S15,C14,A4B4,S22,C22); 
fa37 	: full_adder port map(S16,C15,A5B4,S23,C23); 
fa38 	: full_adder port map(A7B3,C16,A6B4,S24,C24); 
 
-- Stage 4
ha41 	: half_adder port map(S18,C17,P(4),C25); 
fa42 	: full_adder port map(S19,C18,A0B5,S26,C26); 
fa43 	: full_adder port map(S20,C19,A1B5,S27,C27); 
fa44 	: full_adder port map(S21,C20,A2B5,S28,C28); 
fa45 	: full_adder port map(S22,C21,A3B5,S29,C29); 
fa46 	: full_adder port map(S23,C22,A4B5,S30,C30); 
fa47 	: full_adder port map(S24,C23,A5B5,S31,C31); 
fa48 	: full_adder port map(A7B4,C24,A6B5,S32,C32); 
 
-- Stage 5 
ha51 	: half_adder port map(S26,C25,P(5),C33); 
fa52 	: full_adder port map(S27,C26,A0B6,S34,C34); 
fa53 	: full_adder port map(S28,C27,A1B6,S35,C35); 
fa54 	: full_adder port map(S29,C28,A2B6,S36,C36); 
fa55 	: full_adder port map(S30,C29,A3B6,S37,C37); 
fa56 	: full_adder port map(S31,C30,A4B6,S38,C38); 
fa57 	: full_adder port map(S32,C31,A5B6,S39,C39); 
fa58 	: full_adder port map(A7B5,C32,A6B6,S40,C40); 
 
-- Stage 6 
ha61 	: half_adder port map(S34,C33,P(6),C41); 
fa62 	: full_adder port map(S35,C34,A0B7,S42,C42); 
fa63 	: full_adder port map(S36,C35,A1B7,S43,C43); 
fa64 	: full_adder port map(S37,C36,A2B7,S44,C44); 
fa65 	: full_adder port map(S38,C37,A3B7,S45,C45); 
fa66 	: full_adder port map(S39,C38,A4B7,S46,C46); 
fa67 	: full_adder port map(S40,C39,A5B7,S47,C47); 
fa68 	: full_adder port map(A7B6,C40,A6B7,S48,C48); 
 
-- Stage 7 
ha71 	: half_adder port map(S42,C41,P(7),C49); 
fa72 	: full_adder port map(S43,C42,C49,P(8),C50); 
fa73 	: full_adder port map(S44,C43,C50,P(9),C51); 
fa74 	: full_adder port map(S45,C44,C51,P(10),C52); 
fa75 	: full_adder port map(S46,C45,C52,P(11),C53); 
fa76 	: full_adder port map(S47,C46,C53,P(12),C54); 
fa77 	: full_adder port map(S48,C46,C54,P(13),C55); 
fa78 	: full_adder port map(A7B7,C48,C55,P(14),P(15)); 
 
 
end Behavioral;